1. Field of the Invention
The present invention relates to an integrated circuit layout method and program, particularly to an integrated circuit layout method and program that mitigates the effect due to a voltage drop of the power supply wiring.
2. Description of the Related Art
Conventional ASIC design can eliminate a voltage drop due to power supply wiring by making the power supply wiring width and film thickness sufficiently large so as to supply a uniform power supply voltage across the entire chip. Therefore, during the on-chip layout process, precedence is mainly given to inter-cell or inter-function macro connections so that the connection wiring area or the critical path length can be minimized, when performing on-cell layout (floorplanning) of cells or function macros.
FIG. 1 is a plane view showing an example of on-chip power supply wiring. Power supply ring 14 connected to and circumnavigated past a plurality of power supply pins 12, is provided at on the periphery of chip 10, and a plurality of internal power supply wires 15 are also established in a lattice shape. By using this kind of power supply wiring configuration, the power supply voltage supplied from an external source to power supply pins 12 is supplied uniformly within the chip via power supply ring 14 and internal power supply wires 15. The ground-side power supply wiring also has a similar configuration, and a uniform supply voltage and ground voltage are supplied within the chip.
In recent years, to increase the scale of integration and speed of integrated circuits, the transistors and wiring have been made increasingly minute. Accompanying this decrease in size, there is also a tendency for the on-chip power supply wiring to become minuter. In the future, it is expected that as the cross section of the power supply wiring decreases, the voltage drop due to the resistance of the power supply wiring will become impossible to ignore.
FIG. 2 shows a power supply voltage distribution that is expected in the future. Although external power supply ring 14 is shown in FIG. 2, internal power supply wires 15 have been omitted. The interior of power supply ring 14 is integrated circuit layout area 20. The power supply voltage supplied to power supply pins 12, which are established at the periphery of the chip, is distributed to layout area 20 via power supply ring 14 and internal power supply wires 15. However, as the wiring becomes minuter in the future, the resistance of internal power supply wires 15 and other wiring will grow large enough that it cannot be ignored, and the power supply voltage drop will increase.
As shown in FIG. 2, power supply voltage Vcc1 at the four corners of layout area 20, power supply voltage Vcc2 at the centers of the four sides, and power supply voltage Vcc3 in the middle of the layout area and distant from power supply ring 14 will be related, for example, as Vcc1 greater than Vcc2 greater than Vcc3. In other words, as the distance from power supply ring 14 increases, the voltage drops due to the resistance component of the power supply wiring, and the power supply voltage Vcc that is supplied to that area decreases.
Though not shown in the drawings, the same applies to ground voltages. As the ground power supply wiring becomes minuter, the distance from the periphery of a chip becomes larger, and, as a result, the ground voltage supplied thereto increases conversely.
If the power supply voltage Vcc drops as described above, the operating speed of a cell or macro that was located in that area will drop, and it is expected that the chip will be unable to operate as an integrated circuit. In other words, cells or function macros are used as components of the integrated circuit based on the premise that a pre-designed operating speed is achieved. Therefore, if the prerequisite operating speed decreases due to a power supply voltage drop resulting from the layout, there is a possibility that the integrated circuit for which a prescribed operation was expected will be unable to operate. A similar phenomenon is also expected when the ground voltage increases.
An object of the present invention is to provide a layout method and program that can prevent, as much as possible, a chip from being unable to operate as an integrated circuit, even when the power supply wiring becomes minute and the power supply voltage differs according to the on-chip position.
To accomplish the above objective, one aspect of the present invention is that an integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells that are to be laid out in order of their delay times, placing cells having the largest delay times closer to the peripheral area of the chip, and as the cell delay times get smaller, placing the relevant cells closer to the central area of the chip.
A further aspect of the present invention is that an integrated circuit layout method for placing a plurality of function macros within a chip comprises a process for sorting the plurality of function macros that are to be laid out in order of their operating speed margins, placing function macros having the smallest operating speed margins closer to the peripheral area of the chip, and as the function macro operating speed margins get larger, placing the relevant function macros closer to the central area of the chip.
A further aspect of the present invention is that an integrated circuit layout method for placing a plurality of function macros within a chip comprises a process for sorting the plurality of function macros that are to be laid out in order of their operating speed margins, placing function macro having the smallest operating speed margin in the peripheral area of the chip in a first ring configuration, and as the function macro operating speed margins get larger, placing the relevant function macro closer to the central area of the chip in a second ring configuration smaller than the first ring configuration.
By placing cells having larger delay times closer to the peripheral areas of the chip and cells having smaller delay times closer to the central area of the chip, the above invention can prevent the delay time from becoming extremely large causing the integrated circuit to be unable to operate, even if the power supply voltage of the central area decreases or the ground voltage increases thereby resulting in a decrease in the cell operating speeds.
Also, by placing function macros having small operating speed margins closer to the peripheral areas of the chip and function macros having large operating margins closer to the central area of the chip, the above invention can prevent the operating speed margins from becoming extremely tight causing the integrated circuit to be unable to operate, even if the operating speeds of the function macros slow down due to a decrease in the power supply voltage or increase in the ground voltage of the central area.